Aldec Releases Ultra-Fast Verification Environment Customized for Xilinx Devices

Henderson Nevada, January 28th, 2002-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) announced today release of the Xilinx version of its popular Active-HDL design software. Active-HDL 5.1Xilinx Edition (XE) has been developed specifically for high-density Xilinx FPGA devices to ensure that System On Chip (SoC) designers will be able to verify even the most complex devices in minimal time. The Xilinx Edition has been made available to continue to promote the tight partnership between Aldec and Xilinx; an alliance that continues to bring system designers the most advanced technology and devices in the industry.

Active-HDL 5.1 XE supports all Xilinx devices and offers a completely self-contained design entry and verification environment for Xilinx flows and tools; it is an optimal solution for those users who work solely with Xilinx devices. The traditional ease-of-use of Active-HDL tools has been further enhanced by the new design automation features for speedy tracing of processes and signals.

Because Active-HDL 5.1XE has been tailored to Xilinx devices, designers do not have to work outside of the Active-HDL XE environment to reach additional resources. All of the Xilinx libraries and Tcl-based flows can be installed directly from the software, providing a completely integrated environment for Xilinx users.

“The combination of Active-HDL 5.1XE and Xilinx ISE provides designers the tools they need to create, verify and implement their design in any of Xilinx’s industry leading devices, including the new CoolRunner-II, RealDigtal Ultra Low Power CPLDs, low cost Spartan-II FPGAs, and the industry’s largest and fastest Virtex-II Platform FPGAs,” stated Craig Willert, Xilinx Software Product Line Marketing Manager. “Additionally, Active-HDL 5.1 Xilinx Edition enables Xilinx Foundation Series customers to import their schematic designs directly into a powerful HDL environment.”

“Aldec and Xilinx have a large base of mutual customers, so developing Active-HDL 5.1XE was a natural progression in the ongoing partnership between Aldec and Xilinx so that we can continue to support the best interests of our customers. Aldec’s Xilinx-specific version of Active-HDL was developed to offer those customers who deal strictly with Xilinx devices a complete FPGA environment at an attractive price,” stated Megan Moran, Product Marketing Manager for Active-HDL.

Active-HDL 5.1 XE’s Design Flow Manager allows designers to control the entire design process from a single screen. They can seamlessly move from design entry through RTL simulation and logic synthesis to Xilinx implementation tools and timing simulation. Active-HDL 5.1 XE provides Xilinx designers with a design verification tool that supports even the latest Virtex� II Xilinx devices. The support of all devices and software tools participating in the design flow, combined with the high-level of design automation, ensure quality designs and accelerated time-to-market for all Xilinx designs.

Availability
Aldec is now offering Active-HDL 5.1 XE as a keylock license, which includes Aldec’s Xilinx Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL/EDIF or Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.

Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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Contact:        Megan Moran                
Aldec, Inc.                                        
(702) 990-4400 ext. 201                        
meganm@aldec.com